How RAMS and ROMs are read

If you take a look at a standard EPROM or SRAM IC's pinout (and even the data sheet if it's available!) you'll see pins like W*, OE*, and CE* - what do these do?

Well, to read an EPROM or to read and write to a static RAM and NOT to the other chips on the system requires a combination of signals to activate them.

A 6116 SRAM IC is 2k x 8. It has 2 power lines, 8 data lines, 3 control lines, and 11 address lines. If you have 2 of these connected to a CPU that has 16 address lines how do you get the correct one to give you back the data when they are both connected to the same address and data lines? Easy. Decode the upper 5 address lines so that certain combinations of them activate the control lines of the SRAM ICs so the correct one is enabled for data reads and writes at the proper place in the CPUs memory map.

Now when looking at the pinouts you'll see things like OE* (or "OE" with a bar over the top of the letters.) The * or bar over the letters signifies it's an "active low" signal. This means that to activate this line the voltage on the pin drops to a logic low condition - close to ground level voltages.

Let's look at the signals:
OE* = Output Enable. When this signal is low the chip will put it's data on the bus when read.
CE* = Chip Enable. When this signal is low the chip can be read (if OE* is low too) or written to (if W* is low at the same time)
W* = Write. When this signal is low the chip can be written to (if CE* is low too)

This information comes in handy when troubleshooting RAM/ROM problems on game boards. If the board reports the ROM as bad but the ROM checks good when read in an EPROM programmer then check those signal lines! If they aren't correct then the board won't be able to read it. Look for a bad socket (common on old games!), gouges/broken traces, or a bad IC.

Neo Geo MVS boards: Common for bad traces on the control signals for the backup SRAM. This will cause the board to not boot and give a click-click-click from the speakers. This is a "stuck in watchdog" problem. The CPU is getting whacked on the reset line continuously as the system tries to get it to boot. This is because the control signals for the backup SRAM aren't there which is causing the chip's control lines to "float." This float is causing spurious outputs from the backup SRAM chips. The problem is that it's connected directly to the CPU just like the CPU's 'work RAM' and the spurious outputs are causing the CPU to never boot. Fix the traces and the board will boot.

Enjoy!

RJ